The present invention disclosed herein relates to semiconductor devices, and, more particularly, to methods of forming patterns in semiconductor devices.
With a tendency toward a higher integration of semiconductor devices, a technique that is capable of forming patterns having fine sizes beyond an exposure limit may be desirable. Recently, a self aligned double patterning (SADP) technique has been developed, in which first patterns are formed and then second patterns are formed therebetween so that pitches of the patterns can be reduced.
Patterns formed in a cell region of a semiconductor memory device typically have small pitches, while patterns formed in a peripheral circuit region are typically larger than those of the cell region.
When SADP is used to form the cell region and the peripheral circuit region, additional time and effort may be required to design the peripheral circuit region as it is typically more complicated. Often, a peripheral circuit that is designed using SADP may be re-analyzed and corrected according to the results of the analysis.